Reduced Power Dissipation Through

Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be signiicantly reduced by a technique known as truncated multiplication. With this technique, the least signiicant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most signiicant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits. High-speed parallel multipliers are fundamental building blocks in digital signal processing systems 1]. In many cases, parallel multipliers contribute signiicantly to the overall power dissipation of these systems 2]. As transistor counts, clock frequencies, and the desire for portability increase, so does the need for low-power parallel multipliers. Parallel multipliers are typically implemented as either array multipliers 3], 4] or tree multipliers 5]-7]. For both types of parallel multipliers, Booth-encoding can be employed to reduce the number of partial products 8], 9]. Estimates given in 10]-12] indicate that array multipliers dissipate more power than tree multipliers and that Booth-encoded multipliers dissipate more power than multipliers that are not Booth-encoded. Various techniques have been developed to reduce the power dissipation of parallel multipliers. Several of these techniques reduce power dissipation by eliminating spurious transitions 13]-15]. Other research has focused on developing novel multiplier architectures and sign-extension techniques to reduce power dissipation and improve performance 16]-19]. Another approach is to develop low-power 3-2 counters and 4-2 compressors, which are key components in parallel multipli-ers 20]-22]. Although each of these techniques helps reduce power dissipation, further reductions will be needed for future digital signal processing systems. This paper examines reductions in power dissipation that can be achieved through the use of truncated multiplication. Sections 2 gives an overview of truncated multipliers, and Section 3 discusses their implementation. Section 4 compares the power dissipation, delay, and area of truncated multipliers to standard parallel multipliers. Section 5 gives conclusions.